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[Streaming Mpeg4] bit_intealeaver1

Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Platform: | Size: 794 | Author: wenjuner | Hits:

[Embeded-SCM Develop] interleave

Description: 块交织的verilog代码--Verilog code for interleave.
Platform: | Size: 1024 | Author: | Hits:

[Streaming Mpeg4] bit_intealeaver1

Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Platform: | Size: 1024 | Author: wenjuner | Hits:

[GDI-Bitmap] verilog_interleave1

Description: 里面是5个关于交织器的源代码，有兴趣的可以下来学习一下-There is a 5 on the interleaver of the source code, are interested in learning what can be down
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[VHDL-FPGA-Verilog] interleave

Description: 数据交织器 verilog HDL源文件-Data interleaver verilog HDL source file
Platform: | Size: 100352 | Author: 长空 | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
Platform: | Size: 64512 | Author: Yang Jie | Hits:

[VHDL-FPGA-Verilog] counter_interleaver

Description: It is verilog based implementation of interleaver and counter for 0,15,3,7,8,4,2,14
Platform: | Size: 1024 | Author: urvish | Hits:

[source in ebook] interleaver

Description: 交织程序，用verilog编写，主要用于通信当中，希望对大家有帮助-Interwoven program, written in verilog, mainly used for communication among everyone
Platform: | Size: 236544 | Author: 牧童 | Hits:

[Program doc] jiaozhi

Description: 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。 -Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results and conclusions.
Platform: | Size: 1368064 | Author: 林健 | Hits:

[Other] jiaozhi

Description: 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，在DE2平台上实现，在示波器上显示观察。-Complete data communication system Interleaver Design for the design, requirements using Verilog HDL programming, implemented on the DE2 platform, observed on the oscilloscope display.
Platform: | Size: 1370112 | Author: 林健 | Hits:

[Software Engineering] interleaver

Description: 移动通信中信道编码交织器的 Verilog hdl 实现-Verilog hdl mobile communication channel coding interleaver implementations
Platform: | Size: 1024 | Author: 杜欧鸥 | Hits:

[VHDL-FPGA-Verilog] inter_deleaver

Description: This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
Platform: | Size: 2048 | Author: rion | Hits:

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